Signals, Filters & Control — Cheat Sheet

Impedance, resonance, filter response, Bode margins and sampling in one place.

Reactance & impedance

InductiveX_L = 2πfL
CapacitiveX_C = 1/(2πfC)
Series RLCZ = R + j(X_L − X_C)
Magnitude / phase|Z| = √(R² + X²), θ = atan(X/R)
Sign of θ+ inductive (I lags), − capacitive (I leads)

Resonance

Frequencyf₀ = 1/(2π√(LC))
Series QQ = (1/R)√(L/C) — lower R, higher Q
Parallel QQ = R√(C/L) — higher R, higher Q
BandwidthBW = f₀ / Q
Series at f₀Minimum |Z| = R — a short
Parallel at f₀Maximum |Z| = R — an open

First-order filters

RC cornerf_c = 1/(2πRC)
RL cornerf_c = R/(2πL)
At the corner−3 dB (×0.707) and 45° phase
Roll-off−20 dB/decade = −6 dB/octave
Time constantτ = RC = L/R; f_c = 1/(2πτ)
Step response63% in 1τ, 95% in 3τ, 99% in 5τ

Higher order

Roll-off−20n dB/decade for n poles
LC cornerf_c = 1/(2π√(LC))
Butterworth QQ = 0.707 (maximally flat)
PeakingQ > 0.707 peaks at f_c — amplifies the ringing
Order neededn ≥ attenuation(dB) / (20 × decades)

Sampling

Nyquistf_s > 2 f_max
Practical rate5–10× the signal bandwidth
Alias frequency|f_signal − n·f_s|
Anti-aliasFilter BEFORE the ADC — after is too late
Corner placementWell below f_s/2, not at it

Loop stability

Open loopL(s) = plant × controller
Gain margin1/|L| at ∠L = −180°; target ≥ 6 dB
Phase margin180° + ∠L at |L| = 1; target 45–60°
Delay marginPM(rad) / ω_gc — extra dead time tolerable
Dead timeCosts phase, not gain — the invisible margin killer
Bandwidth≈ gain crossover frequency

Decibels

Voltage ratiodB = 20 log₁₀(V₂/V₁)
Power ratiodB = 10 log₁₀(P₂/P₁)
−3 dB×0.707 voltage, ×0.5 power
−20 dB×0.1
−60 dB×0.001

Formula reference — verify against the governing standard. Not a substitute for engineering judgment.